M.A. Romashchenko – Dr.Sc.(Eng.), Professor, 

Department Radio Equipment Engineering and Manufacturing, Voronezh State Technical University

D.S. Seimova – Student, 

Department Radio Equipment Engineering and Manufacturing, Voronezh State Technical University E-mail: dashyli98@mail.ru

This article discusses typical methods of protection against electrostatic discharge, as well as an analysis of the key factors that are important for successful simulation of electrostatic discharge. SPICE circuit-based simulation has a great advantage over the layoutbased electrostatic discharge (ESD) inspection tools. What provides early detection and correction of deficiencies in ESD. It is much easier to make changes at the circuit design level than in the post-topological analysis. The challenge for future ESD modeling is to develop methodologies that incorporate the necessary parasitic effects while retaining preferred schema-based modeling methods. In addition, the main problems for future model development that contribute to protection against electrostatic discharge are presented. Electrostatic discharges (ESD) are the predominant failure mechanism in all products in many semiconductor companies. It is known that ESD brings in millions of dollars in real losses each year and an unknown amount of hidden losses each year. It is estimated that 25% of all component failures are due to electrostatic discharge and electrical overvoltage.

The construction of protection schemes against electrostatic discharge in a limited space and with minimal impact on the normal operation of the integrated circuit is a complex design task. Components such as transistors, diodes, laser diodes, electro-optical devices, and various integrated circuits are quite sensitive to electrostatic discharge. Damage caused by electrostatic discharges occurs at each stage of the manufacture and operation of a component, regardless of its electro-optical type.

As technology advances, there is an increase in the density of electronic components. Reducing the size of the components leads to increased sensitivity to electrostatic discharge, therefore, the need for proper protection against electrostatic discharge increases every day.

The negative effects caused by the impact of ESD on the semiconductor component base of electronic means can be alleviated by applying integrated approaches and technical solutions in terms of protection against ESD discharge. It is highly desirable to carry out ESD modeling at the circuit level in order to prevent the destruction of the element base and to guarantee its protection against electrostatic discharges.

Damage caused by ESD is classified as catastrophic and hidden. Catastrophic damage is such that the device can no longer function. However, when the damage is hidden, the electronic device continues to work even after the termination of the effect of ESD, but over time it degrades and fails prematurely.

Currently, all compact models for modeling electrostatic discharges are individual models. If semiconductor companies, suppliers of electronic design automation systems (EDA) and academic institutions can work together to create standard compact models of devices for working with ESD, then SPICE simulation of ESD can bring much more advantages in developing and testing ESD protection and achieve significant results. Obviously, to do this is another serious problem.

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