A.A. Sukhanov - Student, Moscow Institute of Physics and Technology (State University) E.M. Makarychev - Student, Moscow Institute of Physics and Technology (State University); Engineer, PJSC «Radiofizika» (Moscow) I.A. Grigorev - Head of Sector, PJSC «Radiofizika» (Moscow)

This paper introduces development and specifications study of hybrid DDS-PLL synthesizer with spurs suppression algorithm. The main goal is to reduce DAC non-linearity influence on the synthesizer spectral purity. The work contains results of specifications study of hybrid DDS-PLL-synthesizer with spurs suppression algorithm, which provides optimized DDS frequency sets. While conducting this work existing algorithm was optimized by taking into account existing harmonic level from its number dependence and PLL frequency response. Resulting spectrums was compared on specific frequency point and it was shown that 2 DDS based synthesizer scheme with spurs suppression algorithm effectively suppresses harmonic spurs. The following optimization of existing algorithm leads to further harmonic spur suppression down to previously chosen −100 dBc level. Possibilities for further increasing of spur suppression quality in case of spur level requirements tightening has been shown. Use of one DDS instead of integer divider in PLL feedback didn-t lead to noticeable decrease of output phase noise performance.

 

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