A.V. Bashkirov - Ph. D. (Eng.), Associate Professor, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University M.V. Horoshaylova - Post-graduate Student, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University A.Yu. Savinkov - Dr. Sc. (Eng.), Associate Professor, Deputy Director of Programs, JSC «Concern «Sozvezdie» (Voronez). E-mail: a.savinkov@mail.ru

This article describes the configurable hardware architecture of the decoder for the QC-LDPC code. This VLSI optimized for IEEE 802.11 n standard and achieves throughput of 780 Mbit / s. The requirements to the quality of service and bandwidth of modern wireless communication systems require high-performance error correction schemes. Codes with a low density parity check (LDPC), are the main candidates for the next generation of wireless standards for superior error correction capability. In particular, the quasi-cyclic (QC) LDPC-codes offer high throughput capacity at low decoding complexity of realization, and examined in a variety of wireless standards, e.g., DVB-S2, IEEE 802.16, and IEEE 802.11 n. The increasing use of QC-LDPC-codes requires a configurable architecture of the decoder, which can easily be changed (at compile-time) according to the different requirements of performance and complexity. This article describes the configurable hardware architecture of the decoder for the QC-LDPC-code. This VLSI optimized for IEEE 802.11 n standard and achieves throughput of 780 Mbit / s. The architecture is fully variable configuration LDPC-decoder for quasi-cyclic code based on layered offset-min-sum algorithm send the message. Thanks to a subset of the cyclic shift and a tunable control unit, the proposed architecture can decode virtually any QC-LDPC-code, which is entered in the selected memory. Memory requirements were significantly reduced, while maintaining internal messages from the decoder, which shows to set the balance between the development of the area of performance and the speed of the circuit to reduce the number of errors during development. QC-LDPC-decoder has been optimized for IEEE 802.11 n.

 

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