350 rub
Journal Radioengineering №11 for 2014 г.
Article in number:
Architectural features radeon graphics processors family and their application in the field of resource-intensive simulations of error-correcting codecs
Keywords: parallel computing architecture GPU decoding algorithms error correcting coding
Authors:
A.V. Bashkirov - Ph.D. (Eng.), assistant professor of design and manufacture of radio, Voronezh State Technical University. E-mail: kipr@vorstu.ru
A.M. Belitsky - graduate
A.I. Klimov - Dr.Sc. (Eng.), professor of the chair of info communication systems and technologies, Voronezh Institute of the Interior of Russia. E-mail: kipr@vorstu.ru
Yu.S. Naumenko - graduate student, Voronezh State Technical University. E-mail: kipr@vorstu.ru
A.S. Samodurov - Ph.D. (Eng.), assistant professor of design and manufacture of radio, Voronezh State Technical University. E-mail: kipr@vorstu.ru
V.M. Pitolin - Dr.Sc. (Eng.), professor electric drive, automatic equipment and managements in technical systems chairs «Voronezh state technical university»
Abstract:
This paper deals with the problem of resource- error-correcting codec simulation produced at the preliminary stages of the development of modern means of communication. Considerable time at this stage associated with a large number of simulations produced, due to the variation of parameters necessary codecs and statistical verification. As an approach to solving this problem, we propose the use of parallel computing techniques on graphics processors. Proposes the use of untapped resources of heterogeneous computer systems: in addition to CPU resource (central processing unit, CPU), GPU computing resources ( graphics processing unit, GPU). Considered architectural features video accelerators family Radeon. The results of application of this technique in modeling parameters Convolutional and Low-Density codecs. The results of application of the above approach, demonstrating a significant increase in computing speed using GPU resources with respect to classical simulation on the CPU.
Pages: 15-18
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