D. E. Presnov - Ph.D. (Phys.-Math.), Senior Research Scientist, Department of microelectronics, Skobeltsyn Institute of Nuclear Physics, M.V.Lomonosov Moscow State University. E-mail: denis.presnov@phys.msu.ru
S. V. Amitonov - Post-Graduate Student, Cryoelectronics Lab, Faculty of Physics, M.V.Lomonosov Moscow State University. E-mail: sam-msu@yandex.ru
V.S Vlasenko - Head of Department of Research and Industrial Material Science, OPTEC LLC, Moscow, Russia. E-mail: vlasenko@optecgroup.com
V. A. Krupenin - Ph.D. (Phys.-Math.), Senior Research Scientist, Cryoelectronics Lab, Faculty of Physics, M.V.Lomonosov Moscow State University. E-mail: vladimir.krupenin@phys.msu.ru

Over the past few decades have accumulated great experience in fabrication and study of SET devices. With the development of silicon-based technology for the manufacture of nanoscale devices, it became possible to produce single-electron structures with a high operating temperature, resistivity to mechanical and electrical stress. In the extreme case it is possible to use individual impurity atoms as a working elements of structures. This paper provides a detailed description of the advanced technology for the fabrication of SET transistor nanostructures and presents the results of their experimental study. As a material for the manufacture of single-electron transistors used silicon-on-insulator (SOI) wafers. The top layer of silicon was doped with arsenic to almost metallic conductivity with the help of ion implantation technique. The measured profile depth of As has shown, that implanted impurities are concentrated in the upper layer of silicon with a concentration of about 1020 cm-3. The resistance of the top layer of SOI was ~ 340 Ω/□. Transistor structures were formed in the upper layer of SOI by reactive-ion etching of silicon through a metal mask. The produced samples were subjected to isotropic etching in a series of subsequent processes with intermediate measurements of their characteristics. The main purpose of the ongoing etching processes is the final formation of the transistor elements: resistive bridges («tunnel» junctions) and the island of the transistor. An experimental model of the transistor structure was modified in the series of subsequent isotropic etching processes until the current-voltage characteristic demonstrated the Coulomb blockade region. Measurement of the current-voltage characteristics of single-electron transistors have occurred in the reference mode voltage between the drain and source of the transistor and current measurement at different gate voltages of the transistor. The samples were investigated in the temperature range 4.2 K - 300 K. A specific feature of the behavior of a silicon single-electron transistor in comparison with classic metal structures was detected: a slow decrease in the modulation amplitude at the bias voltages V > Voff. It was suggested that the feature is associated with the structure of the transition of the silicon transistor. The developed method of manufacturing single-electron transistors with high operating temperature differs simplicity and the ability to control their parameters. The advantages of silicon structures, combined with the ability of their integration in silicon technology, allow us to consider a silicon-electron transistor as an operational element of the sensor for local and scanning probe systems with a wide range of applications in scientific research and nanoelectronics.