V. Gaev, P. Matyushin, I. Fefilov

Modern communication systems make high demands on the validity of the information transfer. Error probability reduction may be achieved by a number of methods. For example, power of the transferring signal may be increased. But this way is not always efficient. Using various coding techniques, error probability per bit can go to zero, if code block-s length goes to infinity and SNR is higher than a certain value (Shannon limit). Only two code types have closely approached to Shannon limit: LDPC and turbocodes. Turbocodes, owing to their characteristics, obtained wide spread in modern communication systems, including LTE and WiMAX systems. Double binary circular recursive systematic convolutional (DB-CRSC) turbocode is used in WiMAX systems. DB-CRSC turbocode can provide better noise immunity, comparing with RSC turbocode. However, decoding of this code type requires increasing of the computational resources. In the current paper, analysis of DB-CRSC turbodecoders - architecture for FPGA implementation was made. Turbodecoder-s architecture, which uses less logic resources than traditional architecture, was developed for WiMAX system. New hardware architecture for forward and backward metrics calculation unit was proposed. Hardware-software testing of the developed decoder was conducted.