A.V. Bashkirov - Ph.D. (Eng.), Associate Professor, Department of design and manufacture of radio, Voronezh State Technical University
A.I. Klimov - Dr.Sci. (Eng.), Professor of the Chair of info communication systems and technologies, Voronezh Institute of the Interior of Russia
A.V. Muratov - Dr.Sci. (Eng.), Professor, Head of Department of design and manufacture of radio, Voronezh State Technical University
Y.S. Naumenko - Post-graduate student, Department of design and manufacture of radio, Voronezh State Technical University
V.S. Tsymbalyuk - Ph.D. (Eng.), Consultant JSC «Concern «Sozvezdie»

This article discusses approaches to improve the efficiency of error-correcting coding and its hardware implementation. On the example of low-density codes and problems of their hardware implementation, for their solutions are two approaches. The first  a modification of decoding algorithms, where the most intensive scientific study are attempts to develop suitable for hardware implementation of the decoding algorithms for low-density non-binary codes. The second  a modification of the hardware architecture solutions to increase the efficiency of the existing algorithms for decoding codes. As a promising area of application is considered hardware architecture, allowing a high degree of parallelism. We consider the perspective of the application as a means of hardware platforms based on the GPU. Given the dynamics of growth in GPU performance compared to the same period for the CPU, based on an analysis which concluded the feasibility of using GPU to solve problems, allowing parallelization. The application of GPGPU technology to improve the efficiency of the actual problem - resource-intensive parameters simulations of error-correcting coding of the algorithms.