A.V. Bashkirov, A.V. Muratov

The paper considers the use of error-correcting codes, the rationale for using them not only on chips with fixed logic, but also for programmable logic integrated circuits that allow to implement all the inherent high power turbo hardware encoders and decoders. FPGAs have a drawback - high price, but the undeniable advantages, the ability to hide a secret from competitors new principles error-correcting coding from the competition, as mentioned earlier, the break in the party on a limited new development to create a single party to analyze the feasibility of developing and launching it into a series of. The features of the development of algorithms for error-correcting coding for their subsequent sale on the FPGA, which is the ability to choose the number of memory cells used FPGA resources to achieve the necessary speed or perform implementation with limited resources. Proper preparation of the algorithm allows for FPGA smaller than originally planned, due to improvement of the hierarchical structure. In this article we consider two possibilities for the implementation of encoders FPGA-based architectures which analyzes the impact on the size and speed, in terms of space on a chip developed device: the parallelism of hardware solutions for faster implementation of error-correcting coding functions compared with the programmatic approach. And a consistent architecture that is effective in terms of occupied space on the chip, because its implementation requires a multiplier and an adder. The article can be concluded that, despite the fact that so far in the world created by a great variety of error-correcting codes, which differ in base length, redundancy, structure, functional purpose, energy efficiency, the correlation properties of coding and decoding algorithms, form of the frequency spectrum, digital technology, modern architecture chips, and primarily drives the FPGA developers to create new codes or modify existing ones.