T.E. Mikhailyuk - Post-graduate Student, Ufa State Aviation Technical University E-mail: realotoim@mail.ru S.V. Zhernakov - Dr.Sc. (Eng.), Professor, Ufa State Aviation Technical University E-mail: zhsviit@mail.ru

Most modern implementations of neural network basis is nothing but a simulation modeling of neural network based on the sequential algorithm. However, despite the fact that algorithm implemented on a distributed processor system has a high speed, capabilities of the system are limited both by the serial emulation of neurons by each of processor elements and additional constraints associated with the network size. The performance of such a neural network decreases with increasing of the number of connections and its size. The hardware implementation of the neural network is a multi-processor system in which each neuron is represented by processing element and simulates Turing machine (information processing by each layer occurs sequentially), which reduces the efficiency of use of hardware resources, and leads to network redundancy in general. Thus, it seems to be necessary to develop new approaches for better use of existing hardware in the construction of high-performance neural networks. Despite the large number of configurable logic blocks on a chip the size of the neural network which doesn\'t use con-sequential-cyclic structures as elementary processors (neurons) is limited. Therefore, the task of finding the optimal network topology which uses minimum of chip resources while maintaining its maximum speed is an urgent task. Since the hardware basis of FPGA chip is represented by a matrix structure of logic elements it is advisable to use models of Boolean neural networks. In this regard, as an alternative method of hardware implementation of neural network on FPGA it is suggested to use the developed model, which belongs to the class of Boolean ΣΠ-neural networks (BSPNN). Due to multiplicative processing of input vectors large nonlinearity of conversion and high efficiency of working with linearly non-separable functions are achieved. The difference between obtained BSPNN network and existing ones is a good compatibility with FPGA chips. Furthermore, approach based on BSPNN network allows to use the resources of chip as efficiently as possible. In this paper, we suggest a new approach to implementation of hardware neural networks. A model of optimized neuron and network based on it are presented. This approach is perspective for high-performance versatile machines for neural network processing and requires further research. Work in this area may be associated with the construction of adaptive computing devices, which are able to study the execution of logical operations with enhanced speed. Furthermore, applying of the intelligent approach at the stage of device design can provide acceleration of minimization operations for complicated computing units.

 

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