S.G. Baranov - «Shimko Radioelectronics Scientific Development and Production Centre», JSC L.P. Baryshnikov - «Shimko Radioelectronics Scientific Development and Production Centre», JSC A.Kh. Gilmutdinov - «Shimko Radioelectronics Scientific Development and Production Centre», JSC V.A. Merinov - «Shimko Radioelectronics Scientific Development and Production Centre», JSC

Currently, the start-stop asynchronous data transmission address systems (SADTAS) widely use phase-shift keyed noise-like signals (NLS) with phase modulation according to the law of the pseudorandom sequence (PRS). As a baseband bandwidth for data transmission, these systems use different system sequences, for example, built on the basis of the Walsh system. A message in the SADTAS consists of the sync followed by information and/or command words transmitted by certain symbols by means of phase modulation of the carrier wave by the corresponding PRS. To receive information in SADTAS, you must search the sync, get timing synchronization and decode the rest of the information and command words. Search for the sync is fulfilled by an optimum receiver which, in case of phase-shift keyed signals, contains a word filter coordinated with the sync, a solver and a synchronizer. The optimum receiver receives PNS and eliminates uncertainty in the position of the signal in time. After timing synchronization is established, a decoding device is turned on to extract information contained in the information and command words. The task of decoding is to calculate the vector of the correlation sums of the received signal with each of the applicable set of PRS sequences and to find the maximum value vector. The serial number of the detected maximum value determines the transmitted word. For some SADTAS one of the difficulties arising in the realization of the decoding device is the need to minimize response time for the input signal. It is determined by the time needed to calculate all the correlation sums and the time of searching the maximum vector calculation results. To meet this requirement, it is necessary to use a high-speed decoding device. Another feature of SADTAS is the need to receive signals simultaneously from multiple subscribers. This requires the implementation of a multi-channel decoder, which increases hardware costs proportionally. The goal of this work is to create a multi-channel high-speed decoding device for SADTAS with minimal hardware cost. The paper analyzes the variants of constructing a decoding apparatus for start-stop asynchronous data transmission address sys-tems based on a set of correlators and serial Hadamard transformers, and proposes a new way of developing a multi-channel serial Hadamard transformer with faster performance. The above-mentioned solutions are compared with the proposed multichannel Hadamard transformer for speed, hardware cost and power consumption. The proposed variant of the multi-channel serial Hadamard transformer provides costs and energy consumption comparable with the known serial converter hardware, but has a significantly higher speed and thus less time of searching the maximum value.

 

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