S.F. Tyurin, A.M. Morozov, A.V. Nabatov

Lately the so-called "coarse-grained" configurable logical blocks (CLB) of programmed logical integrated chips (PLIC) are built on the basis of programmed RAM - LUT (Look Up Tables) [1]. The realization is based on perfect disjunctive normal forms (PDNF)?representations of logical systems that need considerable hardware expenses. At the same time the major part of realized logical functions has the number of conjunctions K significantly that are less than the total number of n- sets of binary variables. Disjunctive normal form (DNF) is suggested as realization of logic on the basis of hardware realized APLM-algorithm of programmed logical matrix (PLM) [2 - 5] with the use of functional-tolerant elements (FTE) as basic ones [6, 7]. At the same time apart from significant reduction of hardware expenses, the conditions of renovation of PLIC logic are created even in presence of rejection in every configurable logical block (CLB) during several circles, that undoubtedly decreases the operating speed but permits PLIC to realize a part of the most significant algorithms, enabling decrease of productivity.