I.V. Konovalova - Head, «Concern «Vega»
S.V. Markov - Chief Specialist, «Concern «Vega»
S.S. Syagaev - Engineer, «Concern «Vega»

Realized algorithm of blanking signals received from the underlying surface processes the "frequency-range" matrix obtained at a certain stage of processing of the radar frame. The algorithm is to extract (after pre-filtering) and to blank connected regions of large area, in which the elements of a given fixed threshold is exceeded. In order to compare the performance for this task, the algorithm is realized in the two types of hardware components: at DSP TigerSHARC ADSP-TS 201 S (produced by Analog Devices), that runs at 500 MHz, and on FPGA Stratix III EP3SL150 (produced by Altera), that runs at 150 MHz. Applications have been developed and tested on development kits: ADSP-TS201S EZ-KIT Lite and Stratix III Development Kit. The application for the DSP is written in C language. A matrix size 256×107 containing blanked interference area the size of 850 marks and goals of the total area of 1022 marks was used for the tests. According to test results, it became known that the matrix is processed by the processor using only the internal memory in a variety of addressing modes during 11 ms and 14 ms, using 100 MHz SDRAM during 46 ms. From this time the stage of linear filtering takes about 70% of the total execution time of the algorithm, the threshold processing and search areas of connected markers - about 30%. FPGA application handles the same matrix for 1.7 ms (using 400 MHz QDRII + SRAM), of which the thresholding and Gaussian filtering takes about 10%, and the search for areas of connected markers - 90%. The advantage of FPGA performance is particularly evident at the stage of filtration due to the parallel pipelined execution of all operations. The comparative advantage of the processor DSP TigerSHARC is the ease of development and debugging of applications.