I.V. Orekhova1, A.Yu. Azov2, G.V. Timofeeva3, S.D. Serov4, I.V. Baranova5, A.V. Plotnov6

1–6 FSUE RFNC «All-Russian Research Institute of Experimental Physics» (Sarov, Russia)
1 ivstepanova@vniief.ru, 2 aazov@niiis.nnov.ru, 3 gtimofeeva@niiis.nnov.ru, 4 sdserov@vniief.ru, 5 petreeva@mail.ru, 6 aplotnov@niiis.nnov.ru

Statement of the problem. To implement FeRAM non-volatile memory chips based on ferroelectric capacitors, various memory cell variants compatible with CMOS technology are used. In the traditional version, the storage element is a MIM capacitor and is located above the transistor drain. A significant disadvantage of this memory cell design is the destructive method of reading stored data, which leads to a change in polarization and requires rewriting, which reduces the possible number of rewriting cycles. The development and production of ferroelectric memory cells with a non-destructive reading method is an urgent problem today. In this work, a memory cell is developed and studied, in which the storage element is located above the gate. This method of organizing a memory cell facilitates non-destructive reading, as the reading is performed using the drain current. Changing the polarization state of the ferroelectric leads to the modulation of the surface potential of the semiconductor and, accordingly, the opening or closing of the transistor's conducting channel. The use of such a memory cell design is potentially beneficial for miniaturization.

Objective. To evaluate the feasibility of implementing a non-destructive read-only FeRAM memory cell based on hafnium-zirconium oxide films by placing the storage element above the transistor's gate.

Results. The performance of the cell with the storage element placed above the gate at voltages in the threshold region is demonstrated. During the reading process, the difference in the drain current of the transistor between the logical states of "1" and "0" was recorded, which was 10 μA at a voltage of 0.7 V, demonstrating the operation of the memory cell.

The effect of activation voltage on the operation of memory cells is investigated. It is revealed that the highest current difference during reading of logical levels is recorded when using a voltage of 3.2 V.

Practical significance: The obtained results can be further used when developing non-volatile FeRAM chips with non-destructive reading, which significantly increases the possible number of rewrite cycles and reduces the area occupied by the storage elements, and thus the size of the chip.

Orekhova I.V., Azov A.Yu., Timofeeva G.V., Serov S.D., Baranova I.V., Plotnov A.V. Research of storage elements based on ferroelectric for the production of non-volatile memory (FeRAM). Achievements of modern radioelectronics. 2026. V. 80. № 1. P. 60–66. DOI: https://doi.org/10.18127/j20700784-202601-06 [in Russian]

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