350 rub
Journal Achievements of Modern Radioelectronics №12 for 2018 г.
Article in number:
Double-pipelined architecture of a real-time recurrent noise filtering
Type of article: scientific article
DOI: 10.18127/j20700784–201812–23
UDC: 004.272.22
Keywords: pipeline signal processing FPGA interference filtering.
Authors:

A.V. Sokolovskiy – Research Scientist, Siberian Federal University (Krasnoyarsk)

E-mail: sokolovskii_a@mail.ru

I.V. Tyapkin – Teacher of Faculty, Siberian Federal University (Krasnoyarsk)

E-mail: Aronakss@yandex.ru

E.A. Veisov – Professor, Siberian Federal University (Krasnoyarsk)

E-mail: eveisov@sfu-kras.ru

Abstract:

The article presents a study of the method of double pipelining for the hardware implementation of a recurrent algorithm for filtering a signal from a phased antenna array from interference.

 

Pages: 112-115
References
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  2. Behrooz Parhami Algorithms and Design Methods for Digital Computer Arithmetic. 2012.
  3. Xilinx UG1046, UltraFast embedded Design Methodology Guide. 2015.
  4. Perov A.I., Kharisov V.N. GLONASS principih postroeniya i funkcionirovaniya / Izd. 4-e, pererab. i dop. M.: Radiotekhnika. 2010.
  5. Ifeachor E.C., Jervis B.W. Digital Signal Processing. A Practical Approach / 2nd ed. Upper Saddle River, NJ: Prentice Hall. 2002.
  6. Dzhigan V.I. Adaptivnaya filjtraciya signalov: teoriya i algoritmih. M.: Tekhnosfera. 2013.
Date of receipt: 15 ноября 2018 г.