A.A. Feimov - Post-graduate Student, Engineer, JSC «All-Russia SRI of Radio Engineering» (Moscow). E-mail: afeimov@gmail.com E.P. Smirnov - Ph. D. (Eng.), Head of Sector, JSC «All-Russia SRI of Radio Engineering» (Moscow). E-mail: vornims@gmail.com P.E. Shimkin - Post-graduate Student, Engineer, JSC «All-Russia SRI of Radio Engineering» (Moscow). E-mail: shimkinpy@gmail.com

In recent years, the development of phased array antennas has led to a significant increase in functionality of radar stations, and subsequent replacement of analog to digital receivers make better use of adaptive beamforming algorithms that enable using adaptive weighting factors to solve the problem of optimal spatial processing. The basic idea is to adapt the formation of «zeros» in the receiving antenna pattern in the directions of noise sources, i.e. the imple-mentation of spatial filtering. To do this, adaptively tunable calculate optimal ratios. Represents additional complexity and need for rapid conversion coefficients for surveillance radars with mechanical rotation in azimuth, as the direction of interference and can change it simply ceases to be filtered, coming from the area of suppression. In other words, the calculation of new coefficients should be faster than the rotation of the radar at an angle equal to the width of the zones of inhibition. This time may be tens-hundreds of microseconds depending on the speed of rotation of the radar. In this paper we show that for solving adaptive spatial filtering surveillance radar with mechanical rotation in azimuth is the most ap-propriate algorithm for matrix inversion using a modified method of turning quadratic Givens (MSGR - Modified Squared Givens Rota-tions). FPGA families such as Arria and Stratix from Altera or Xilinx Virtex company can realize fully parallel systolic array to be inverted. Performance and FPGA architecture should be selected based on the size of the matrix and the desired speed of its appeal. As an example, in this study we considered the possibility of the implementation of this algorithm for the matrix size 11×11, using FPGAs Arria V GX family firm Altera. When using numbers in the format of a single precision floating point calculation may produce a similar 12 microseconds posted 7 FPGA chips.

 

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