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Journal Achievements of Modern Radioelectronics №7 for 2011 г.
Article in number:
Video Encoder Ip Core Designed for Sub-Micron System on Chip Integrated Circuits
Keywords: IP core PAL/ NTSC video encoder DAC modulator chip layout
Authors:
P. S. Khabarov, D. L. Shlemin, V. D. Lys, Y. P. Lebedev, V. Yu. Vasilyev, Yu. N. Popov, Yu. N. Chepin
Abstract:
A three-channel multi-standard PAL/NTSC mixed-signal video encoder IP core for digital TV and multimedia applications has been designed. The IP core has been manufactured using a standard 0.18 µm CMOS technology flow with analog options. In this paper, the results of the IP core investigation are presented. A few chip scanning electron microscopy cross-sectional images are shown. Total power dissipation has been measured to be 89 mW. Measured DAC parameters show truly 10 bit 27 MHz performance. The measured integral nonlinearity and differential nonlinearity are ±0.7 LSB and ±0.35 LSB, respectively. Area of use of this integrated circuit leads from consumer digital TV to a security applications and some special use. This chip design can be used for digital to analog video encoding either separately, or as an IP core. Results obtained confirmed the used algorithm of mixed signal circuit design.
Pages: 54-59
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