350 rub
Journal Achievements of Modern Radioelectronics №7 for 2009 г.
Article in number:
Problems of Scaling of CMOS VLSI Characteristics
Authors:
N.V. Masalsky
Abstract:
Achievements of semiconductor VLSI manufacturing techniques simultaneously with increase of a degree of integration complicate a problem of scaling of their physical characteristics. The stated qualitative and quantitative laws of the theory of scaling allow one to solve effectively problems of development and creation of modern electronic devices. At transition to transistors with small length of gate in nanometer areas are more sharply shown the physical restrictions connected to absence of scaling of separate parameters and their critical influence. For ultra thin thickness of working silicon layers of transistors, switching transistors, great value get already quantum effects, in particular effects of dimensional quantization of a power spectrum of carriers.
Pages: 3-27
References
  1. Frank, D.J., Dennard, R.H., Nowak, E., Device Scaling Limits and their Application Dependencies // IEEE Proc. 2001. 89(3). Р. 259-287.
  2. Boeuf, F.; Sellier, M.; Farcy, A.; Skotnicki, T., An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation // IEEE Trans. Electron Devices. 2008. 55(6). Р. 1433-1440
  3. Wong, H.-S. P., Frank, D.J., Solomon, P.M., Nanoscale CMOS // IEEE Proc. 1999. 87(6). Р. 537-570.
  4. Khakifirooz, A., Antoniadis, D.A., MOSFET Performance Scaling-Part II: Future Directions // IEEE Trans. Electron Devices. 55(6). 2008. P. 1401 - 1408.
  5. Bondy, P.K., Moore-s law governs the silicon revolution // IEEE Proc. 1998. 86(1). Р. 78-81.
  6. Nikolic, B., Design in the Power-Limited Scaling Regime // IEEE Trans. Electron Devices. 2008. 55(1). Р. 71-83.
  7. Razavi, B., A Millimeter-Wave Circuit Technique // IEEE Journal Solid-State Circuits. 2008. 43(9). Р. 2090-2098.
  8. Konstadinidis, G.K., Tremblay, M., Chaudhry, S., Rashid, M.; Lai, P.F., Otaguro, Y., Orginos, Y., Parampalli, S., Steigerwald, M., Gundala, S., Pyapali, R., Rarick, L.D., Elkin, I., Ge, Y., Parulkar, I.,Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor //IEEE Journal Solid-State Circuits. 2009. 44(1). Р. 7-17.
  9. Teh, C. K.; Hamada, M.; Fujita, T.; Hara, H.; Ikumi, N.; Oowaki, Y., Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems // IEEE Trans. Very Large Scale Integration (VLSI) Systems. 2006. 14(12). Р. 1379-1383.
  10. Colinge J.-P., Silicon-On-Insulator Technology: Materials to VLSI. KluwerAcad. Publ. Boston. Dordrecht. London. 1997.
  11. Масальский, Н.В., Захаров, С.М. Моделирование характеристик  логических элементов, выполненных на полностью обедненных КНИ КМОП-нанотранзисторах // Электромагнитные волны и электронные системы. 2007. Т. 10, № 12. С. 66-70.
  12. Сейсян Р. Нанолитография СБИС в экстремально дальнем вакуумном ультрафиолете // ЖТФ. 2005. 75(5). С. 1-13.
  13. Киреев В. Технология и оборудование для производства интегральных микросхем. Состояниеиосновныетенденцииразвития // ЭлектроникаНТБ. 2004. № 7. С. 72-77.
  14. Doyle, B., Arghavani, R., Barlage, D., Transistor Elements for 30 nm Gate Lengths and Beyond // INTEL Technology Journal. 2002. 6(2). Р. 44-53.
  15. Baccarani, G., Wordeman, M.R., Dennard, R.H., Generalized scaling theory and its application to a 1/4 micrometer MOSFET Design // IEEE Trans. Electron Devices. 1984. 31(3). Р. 452-466.
  16. Fiegna, C., Iwai, H., Wada, T., Scaling the MOS Transistor Below 0.1 mm, IEEE Trans. Electron Devices. 1994. 41(6). Р. 941-950.
  17. Dennard, R.H., Gaensslen, F.H., Yu, H.N., Design of ion-implanted MOSFETs with very small physical dimensions // IEEE Journal Solid-State Circuits. 1974. 9(2). Р. 256-262.
  18. Taur, Y., Buchanan, D., Chan, W., CMOS Scaling into the Nanometer Regime // IEEE Proc. 1997. 85(5). Р. 486-504.
  19. Saxena, S., Hess, C., Karbasi, H., Rossoni, A., Tonello, S., McNamara, P., Lucherini, S., Minehane, S., Dolainsky, C., Quarantelli, M.,Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies // IEEE Trans. Electron Devices. 2008. 55(1). Р. 131-144.
  20. Mi-Chang Chang; Chih-Sheng Chang; Chih-Ping Chao; Ken-Ichi Goto; Meikei Ieong; Lee-Chung Lu; Diaz, C.H.,Transistor-and Circuit-Design Optimization for Low-Power CMOS // IEEE Trans. Electron Devices. 2008. 55(1). Р. 84-95.
  21. Taur, Y., Ning, T., Fundamentals of VLSI Devices. Cambridge University Press. Cambridge. UK. 1998.
  22. Thompson, S., Alavi, M., Hussein, M., 130 nm Logic Technology Featuring 60 nm Transistors, Low-K Dielectrics, and Cu Interconnects // INTEL Technology Journal. 2002. 6(2). Р. 5-12.
  23. Масальский Н.В. Механизмы, определяющие разброс пороговых напряжений КНИ КМОП-транзисторов // Успехи современной радиоэлектроники. 2008. № 7. С. 31-42.
  24. Ge, L., Fossum, J.G.,Analytical modeling of quantization and volume inversion in thin Si-film double-gate MOSFETs // IEEE Trans. Electron Devices. 2002. 49(2). Р. 287-294.
  25. Trivedi, V., Fossum, J.G., Scaling Fully Depleted SOI CMOS // IEEE Trans. Electron Devices. 2003. 50(9). Р. 2095-2103.
  26. Zakheim, D.A., Gurevich, S.A.,  Rozhansky, I.V., Two Types of Granular Metal Films Applicability for Field-Effect Devices // Surface Science. 2003. 532(10). Р. 1187-1192.
  27. Chalvatzis, T.; Yau, K.H.K.; Aroca, R.A.; Schvan, P.; Ming-Ta Yang; Voinigescu, S.P., Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS //IEEE Journal Solid-State Circuits. 2007. 42(7). Р. 1564-1573.
  28. Horowitz, M. Ho, R., Mai, K., The Future of Wires. Department of Electrical Engineering Stanford University. CA, paperpreparedforSRC. May 1999.
  29. Горячев В.А. Масштабирование линий связи для проектирования нанотранзисторных КМОП СБИС // Электромагнитные волны и электронные системы. 2008. Т. 13.№ 2-3. С. 111-119.
  30. Yamamoto, H., Davis, J.A., Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation // IEEE Trans. Very Large Scale Integration (VLSI) Systems. 2007. 15(6). Р. 649-659
  31. Junmou Zhang, Friedman, E.G., Crosstalk modeling for coupled RLC interconnects with application to shield insertion // IEEE Trans. Very Large Scale Integration (VLSI) Systems. 2006. 14(6). Р. 641-646.
  32. Alioto, M., Palumbo, G., Poli, M., Energy consumption in RC tree circuits // IEEE Transactions Very Large Scale Integration (VLSI) Systems. 2006. 14(5). Р. 452-461.
  33. Zuber, P., Bahlous, O., Ilnseher, T., Ritter, M., Stechele, W., Wire Topology Optimization for Low Power CMOS //IEEE Trans. Very Large Scale Integration (VLSI) Systems. 2009. 17(1). Р. 1-11.
  34. Mukhopadhyay, S., Keunwoo Kim Jenkins, K.A., Ching-Te Chuang, Roy, K.,An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process // IEEE Journal Solid-State Circuits. 2008. 43(9). Р. 1951-1963.
  35. Sathe, V. S.; Chueh, J.-Y.; Papaefthymiou, M C.,Energy-Efficient GHz-Class Charge-Recovery Logic // IEEE Journal Solid-State Circuits. 2007. 42(1). Р. 38-47.
  36. Duarte, D., Impact of Scaling on The Effectiveness of Dynamic Power reduction schemes. 20th International Conference on Computer Design. 2002.
  37. Voorde, P.V., MOSFET Scaling into the Future. Hewlett-Packard Journal. August 1997.
  38. Thompson, S., Packan, P., Bohr, M., MOS Scaling: Transistor Challenges for the 21st Century // Intel Technology Journal. 1998. 2(3). Р. 14-21.
  39. Wei, L., Roy, K., Multiple Vth CMOS for Leakage Control in Deep Submicron IC-s. Technical Report CE_ME99-5, Princeton Univ. Dept. of Elect. Eng. 1999. Р. 1-15.
  40. Noda, H., Nakajima, M., Dosaka, K., Nakata, K., Higashida, M., Yamamoto, O., Mizumoto, K., Tanizaki, T., Gyohten, T., Okuno, Y., Kondo, H., Shimazu, Y., Arimoto, K., Saito, K., Shimizu, T.,The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture // IEEE Journal Solid-State Circuits. 2007. 42(1). Р. 183-192.
  41. Landman, P.E., Low-Power Architectural Design Methodologies. University of California at Berkeley. 1994.    
  42. Pedram, M., Power Simulation and Estimation in VLSI Circuits. University of Southern California. 1998.
  43. Gunther, S.H., Binns, F., Carmean D.M., Hall J.C., Managing the Impact of Increasing Microprocessor Power Consumption // Intel Technology Journal. 2001. 5(1). Р. 25-34.
  44. Montanaro, J., Witek, R.T., Anne, K., Black, A.J., Cooper, E.M., Dobberpuhl, D.W., Donahue, P.M., Eno, J., Hoeppner, W., Kruckemyer, D., Lee, T.H., Lin, P.C.M., Madden, L., Murray, D., Pearce, M.H., Santhanam, S., Snyder, K.J., Stehpany, R., Thierauf, S.C.,A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor // IEEE Journal Solid-State Circuits. 1996. 31(11). Р. 1703-1714.
  45. Rakhmatov, D., Energy Budget Approximations for Battery-Powered Systems With a Fixed Schedule of Active Intervals // IEEE Trans. Very Large Scale Integration (VLSI) Systems. 2008. 16(8). Р. 985-998.
  46. Tivari, V., Dynamic Power Management for the TORCH Superscalar Microprocessor Technical Report CE_ME96-5. Princeton Univ. Dept. of Elect. Eng. 1996. Р. 25-42.
  47. Benini, L., Bogliolo, A., De Micheli, G. Survey of design techniques for dynamic power management // IEEE Trans. Very Large Scale Integration (VLSI) Systems. 2000. 8(3). Р. 299-316.
  48. Microsoft OnNow: The evolution of the PC platform, www.microsoft.com/hwdev/pcfuture/OnNOW.htm.
  49. Intel, Microsoft and Toshiba. Avanced configuration and power interface specification, www.intel.com/ial/powermgm/specs.html .
  50. Geppert, L., Perry, T.S., Transmeta-s Magic Show [microprocessor chips] // IEEE Spectrum. 2000. 37(5). Р. 26-33.