S.O. Bykov - Post-graduate Student, Vladimir State University named after A.&N. Stoletovs. E-mail: sobykov@gmail.ru S.G. Mosin - Ph. D. (Eng.), Associate Professor, Department of Computer Engineering, Vladimir State University named after A.&N. Stoletovs. E-mail: smosin@ieee.org

On-chip interconnection networks or Networks-on-Chip (NoC) have been proposed as a solution for addressing the global communication challenges in System-on-Chip architectures that are implemented in nanoscale technologies. Standard topologies are well suited for homogeneous systems, but in general it is more effective to design custom network topology, which will take into account features of a specific system. This paper describes the automated design technique for networks-on-chip with custom topology, which complements the design flows of standard CAD tools. The whole custom topology design process can be divided into six stages: 1. Converting input description into a form, applicable for automatization. 2. Resource mapping. The resources of a system (processing or storage cores) are placed onto chip tacking into account the required bandwidth for connections between them at this stage. 3. Router mapping. At this stage each resource is connected to one router, which is located at the corners of the resource. 4. Virtual channels creation. The calculation of the routing tables for all routers is performed at this stage. 5. Parameter estimation. 6. Generating of output HDL-description. For experimental verification, test design using described technique was done. The MPEG 4 decoder was selected as a designed system. The same system was designed with using mesh topology in order to evaluate the efficiency of the proposed solution. Experimental results have shown, that the solution based on custom topology has allowed to reduce the number of switches by 56% and the number of lines by 72%. However, it should be noted that due to reduction of the number of switches in the custom topology, redundant paths number is reduced. These features affect to the reliability of designed system.

 

1. Mosin S.G. Sovremennye tendencii i tekhnologii proektirovanija integralnykh skhem // Informacionnye tekhnologii. 2009. № 1. S. 28 33.
2. Jantsch A., Tenhunen H. Networks on Chip. KluwerAcademicPublishers. 2003. 312 p.
3. Rantala V., Lehtonen T., Plosila J. Network on Chip Routing Algorithms // TUCS Technical Report. 2006. № 779. 34 p.
4. Schoeberl M., Brandner F., Sparso J. A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems // Proc. NOCS-12. 2012. P. 152−160.
5. Srinivasan K., Chatha K.S., Konjevod G. Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms // Proc. ASP-DAC \'07. 2007. P. 184−190.
6. Srinivasan K., Chatha K.S. ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis // Proc. VLSID-05. 2005. P. 623−628.
7. Mosin S.G. Md Muid Hassan Design flow Oriented on INOC // Proc. of Second International Conference on Signals, Systems & Automation (ICSSA-11). 2011. P. 281−284.
8. Bykov S.O. Algorithm for automated custom Network-on-Chip topologies design // Proc. EWDTS-2013. P. 1−3.
9. Bykov S.O. Avtomatizacija proektirovanija setejj-na-kristalle so specializirovannojj topologiejj // Sb. trudov. «Problemy razrabotki perspektivnykh mikro- i nanoehlektronnykh sistem». 2014. CH. 2. S. 21−24.
10. Gebali F., Elmiligi H., El-Kharashi M.W. Networks-on-chips: theory and practice. Taylor & FrancisGroup, LLC. 2009. 355 p.
11. Srinivasan K. An automated technique for topology and route generation of application specific on-chip interconnection networks // Proc. ICCAD-05. 2005. P. 231−237.