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Design of Digital FIR-filters on Programmable Logic Devices


V.G. Agakov, А.А. Nosov, M.Yu. Myagchilov, S.V. Abramov

The article deals with the design route of the digital FIR-filters of the different orders on the Xilinx PLD Spartan-3E of the FPGA family using the weighing method (the «window» method). Filter realization on the PLD Spartan-3E allows good capacity to be achieved as compared to the other realization methods. It results from the on-chip elements and parallel signal processing. The FIR-filter mathematical model has been created in the MATLAB/Simulink medium. Then it has been transferred to the medium of the design physical synthesis on the FPGA by means of the CAD ISE and SystemGenerator package. This method does not require the step of debugging and error eliminating. The analysis of different window function has been performed in the process of designing. As a result the Blackman window has been chosen, because this function has stronger attenuation in the suppressed frequency range. The FIR-filter of the Direct Form Symmetric FIR structure has been configured into the PLD XC3S500E-4FG320 chip, the chip resources occupied by the filters of different orders have been evaluated.

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