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Interconnects scaling of CMOS VLSI at transition to new technological norms



In this paper, according to domestic prospects of development silicon on isolator (SOI) technologies for limits < 0,1 microns of the technological sizes, transformations of physical parameters interconnections very large schemes integrated (VLSI) in various variants of scaling are considered. Delays and restrictions of throughput global and local models of the connections, compatible delays are discussed with similar scaling. Decrease in the sizes of cross-sections conductors and about equal to them of thickness dielectric layers does not reduce time of delay in communications. The given conclusion has the general character and essential impact on characteristics of interconnections makes at scaling. Moreover, decrease in the sizes of sections conductors and dielectrics in nanosizes area leads to growth of technological heterogeneity and increase in resistance and capacity of conductors. Display structure a surface of materials at decrease in nanosizes area of elements leads to degradation of conductivity and growth of mutual capacity interconnections. Therefore the choice of optimum technology becomes complicated in process growth degrees of integration transistors elements in VLSI that leads to various improvements, including a principle of "return scaling» global connections and transition to 3 dimensional structures. In final section of this work limiting conditions of increase in speed nano SOI VLSI are presented at a food voltage reduc-tion, degradation processes and preservation of safety in operation connections.
May 29, 2020

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