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Low power 1-bit full adder characteristics for fully depleted SOI CMOS nanotransistors

Keywords:

N.V. Masalsky


Ultra-thin-body SOI (silicon-on-insulator) nanotransistors are one of the most promising candidates for future low power and high performance applications. In a range of supply voltage less than 1 V characteristics of physical model of the one-bit adder executed on thin-film fully depleted CMOS SOI nanotransistors with channel length of 40 nanometers are analysed. In a range where adjustment of a threshold voltage is possible, dependence of a delay on displacement on the back gate has linear character in all researched area of supply voltage. At increase of a voltage on the back gate the value of a delay linearly decreases. It allows to operate effectively a delay of the device without change of active capacity. The steepness of the given dependence is determined by the relation of thickness face-to-face and return gate transistors. And the it is more, the more effectively adjustment of a delay. At a voltage reduction of supply voltage the range of adjustment of a delay decreases in the nonlinear image. The marginal level of active capacity does not exceed 20 мкВт, static 33 нВт. The minimum of product « delay - energy of switching » is in area a supply voltage more essentially below 1 V. His position does not depend from a set of entrance signal.
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