V.M. Dyakonov, A.V. Korshunov, A.V. Marinych
One of challenge with CMOS technology scaling is the rapid increase of chip consumption power. It is needed to develop new design methodology to reduce power consumption. New methodology will minimize power without area or performance penalty.
There are two kinds of power dissipation in synchronous CMOS VLSI: dynamic and power. In this paper, we consider dynamic power optimization methods. Dynamic power dissipation includes the capacitive power that is associated with the switching of logic values in the IC. This component is proportional to load capacitance, clock frequency, supply voltage and switching activity. Also dynamic power includes the direct path current path between Vdd and GND bus for a short period of time during switching. We describe method of minimization short-circuit current by matching the rise/fall times of input/output signals.
Capacitive power is most significant component of dynamic power for state-of-the-art VLSI and SoC. In this paper we describe methods optimization all parameters of capacitive power. For supply voltage minimization – static voltage scaling and dynamic voltage scaling. Optimization methods of clock frequency are parallelization and dynamic voltage and frequency scaling. Optimal approach to reduce load capacitance and switching activity is use precomputation logic, retiming and clock gating.
In conclusion we are analyzing the efficiency of dynamic power optimization methods. Also we are considering the efficiency power optimization methods for nanometer CMOS technology.