fully depleted SOI nanotransistor
low supply voltage
Ultra-thin-body SOI (silicon-on-insulator) nanotransistors are one of the most promising candidates for future low power and high performance applications. The problems of regulation of delay and bound with her of switching energy of the logic gates inverter, 2NAND 2NOR physical models for fully depleted SOI CMOS nanotransistors in the field of power supply voltage less 1 V are considered. The regulation implements through varied values of the back gate voltage of transistors. For the inverter the analytical evaluations of steepness of a control characteristic and adjustment range are obtained. Thus the steepness is determined by relation of thicknesses frontal and back gates of transistors. And the it is more, the more effective adjustment. The relation of delay to displacement on the back gate has linear nature for analyzed power supply voltage range. With decreasing of power supply voltage the adjustment range of delay is narrowed down, however steepness remains practically to constant. The numerical evaluations and the program HSPICE simulation results of the switching characteristics investigated logical gates executed on nanotransistors with length of a channel L = 40 nm and Si-body thickness 4.7 nm are compared. The boundaries of feasibility of the obtained evaluations are determined and their practical significance is marked. Generally logic gate 2NAND steepness of a control characteristic is greatest, inverter is least. At reduction of power supply voltage the decreasing of adjustment range of delay for all investigated elements has non-linear nature. From simulation results as follows, that the minimum of product «delay - energy of switching» is reached in area power supply voltage less than 1 V. It’s position does not depend on a gate logical function. At reduction of power supply voltage the decreasing of adjustment range of parameter «the delay - energy of switching» for all investigated valves has non-linear nature.