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Soft decision forward error correction application in optical transport networks

DOI 10.18127/j20700784-201812-25

Keywords:

S.V. Ovsyankin – Ph.D. (Eng.), Academy of FSO of Russia
А.А. Proskurin – Ph.D. (Eng.), Academy of FSO of Russia
V.O. Yudin – Employee, Academy of FSO of Russia
S.U. Kostomarov – Employee, Academy of FSO of Russia
E-mail: interleaver@mail.ru


Taking into account the tendencies of optical transport networks development, i.e., permanent increasing of backbone data rates, and considering the long haul of communication links, it is obvious that the noise immunity of user traffic becomes critical. In these conditions the new generation codes come to application in addition to the classic FEC schemes of 40G optical systems. These codes give extra net coding gain while using relatively simple processing and allow data transfer rates beyond 100 Gbit/s. The classic OTN coding schemes are, first of all, Reed-Solomon code (ITU-T G.709 rec.) as well the cascade schemes based on BCH and RS (ITU-T G.975.1 rec.). Such codes using for redundancy data the relevant fields of optical transport units and for error correction – hard decision algorithms, are called HD-FEC. New generation codes, using OTU block entirely for encoding and soft decision algorithms for decoding, are called SD-FEC. This type of coding is not standardized and often is peculiar to specific equipment.
There are several reasons for application in OTN for data rates beyond 100 Gbit/s exactly such codes.
Firstly, such fiber optical systems utilize the transfer of phase modulated signals (usually also polarization divided). The application of phase modulation let demodulator compute the soft likelihood metrics.
Secondly, SD-FEC decoding algorithms are iterative, and the symbol metrics are become more precise every repetition. Repetitions are relatively simple and provide an assured transfer delay. Quantity of repetitions is regulated depending on channel rate and quality of service demands.
Thirdly, codes of such type (LDPC, for example) frequently have easy-to-realize (in FPGA and ASIC) structures: the repeated parts (so called «circulants») are presented in parity check matrix. These circulants permit to produce the parallel computations of intermediate results during one algorithm iteration, and also to save memory economically placing parity check equations. It is especially typical for quasi-cyclic LDPC codes.

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June 24, 2020
May 29, 2020

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