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Using Vivado High Level Synthesis for domestic cryptography cipher implementation

DOI 10.18127/j20700784-201812-19

Keywords:

А.Е. Gordeev – Design Engineer, JSC «SPE «Radiosvyaz» (Krasnoyarsk)
E-mail: sinclair55@yandex.ru
I.V. Anikev – Head of Department, JSC «SPE «Radiosvyaz» (Krasnoyarsk)
E-mail: ivananik82@gmail.com


The FPGA design approaches have moved through a few abstraction levels, to manage the complexity of the designs. Each new abstraction level hides some of the complexity of design implementation step, offering productivity at the cost of less visibility in the challenges associated with the lower abstraction level.
• A transistor layout database hides the challenges in mask making and wafer processing. The focus of the layout abstraction layer is to respect Design Rule Checks (DRC) which models the basic layout.
• For FPGA design, a netlist avoids a detailed layout effort: the netlist is constructed with instances from a pre-built library. The focus of the netlist abstraction layer is to define the Boolean functionality of the design with appropriate area, performance and power.
• A Register Transfer Level (RTL) description captures the desired functionality by defining datapath and logic between boundaries of registers. RTL synthesis creates a netlist of Boolean functions to implement the design. The focus of the RTL abstraction layer is to define a model for the hardware which is functionally correct.
• A functional specification removes the need to the define register boundaries (and the specific logic required between them) to
implement the desired algorithm. The focus of the designer is only on specifying the desired functionality.
As with previous moves up the abstraction level, using a functional specification with high-level synthesis (HLS) to automatically create the RTL design provides productivity benefits in both verification and design optimization.
The significant benefits of acceleration in simulation time by using a functional C language based specification and the resultant earlier detection of design errors has been embraced for quite a while.
• High Level Synthesis shortens the previous manual RTL creation process and avoids translation errors by automating the creation of the RTL from the functional specification.
• High Level Synthesis automates the optimization of the RTL architecture, allowing multiple architectures to quickly and easily be evaluated before committing to an optimum solution.

References:
  1. Vivado Design Suite High-Level Synthesis (UG902). URL: https://www.xilinx.com/support/documentation/sw_manuals/xil-inx2018_2/ug902–vivado-high-level-synthesis.pdf.
  2. GOST R 34.12–2015. Informacionnaya tehnologiya. Kriptograficheskaya zaschita informacii. Blochnye shifry. Vved. 2015–06–19. M.: Standartinform. 2015.
June 24, 2020
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