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Application of sample and hold circuits in devices digital to analog conversion

DOI 10.18127/j00338486-201812-07

Keywords:

A.S. Gruzdev – Ph.D.(Eng.), Associate Professor, Department «Radio Electronic Information Security Systems»,  Peter The Great St. Petersburg Polytechnic University
E-mail: gruzdev@cee.spbstu.ru


The new modification of the output stage IC DAC with parallel structure is proposed. It contains a sample-and-hold circuit which allows to reduce glitch to a value less than 0.5 nV•sec. The proposed scheme provides 20-bit monotonic conversion and 2 microseconds settling time.

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May 29, 2020

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