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Heterogeneous multicore system on chip with 512 Gflops peak performance

DOI 10.18127/j20729472-201803-08

Keywords:

A.L. Eisymont – Head of Sector, RC «Module» (Moscow)
E-mail: eisymont@module.ru
V.M. Chernikov – Ph.D.(Eng.), Main Designer – Head of Department, RC «Module» (Moscow)
E-mail: tchern@module.ru
An.V. Chernikov – Head of Sector, RC «Module» (Moscow)
E-mail: chernant@module.ru
Al.V. Chernikov – Deputy Head of Department, RC «Module» (Moscow)
E-mail: achernikov@module.ru
D.E. Kosorukov – Head of Department, RC «Module» (Moscow)
E-mail: dkos@module.ru
I.I. Nasonov – Head of Sector, RC «Module» (Moscow)
E-mail: nasonov@module.ru
A.A. Komlev – Leading Engineer, RC «Module» (Moscow)
E-mail: a.komlev@module.ru


This article is devoted to questions and methods of implementing energy efficient heterogeneous and tolerant to memory latency system on chip (SoC) operating at 1 GHz frequency, with 512 Gflops peak performance and hierarchically organized internal memory. SoC contains sixteen NeuroMatrix NMC4 processor cores and five ARM Cortex-A5. The next step is to master the described architectural features in the software and users. The concepts of carrying out these works are compiled, detailed and under implementation.

References:
  1. Dally W., Balford J. et al. An Energy-Efficient Processor Architecture // IEEE Computer Architecture Letters. Jan. 2008. V. 7. № 1. P. 29−31.
  2. Nowatzki T., Wright G. et al. Pushing the Limits of Accelerator Efficiency While Retaining Programmability // IEEE High performance computer architecture conference. 2016. 13 p.
  3. Durant L., Harris M. et al. Inside Volta: The World’s Most Advanced Data Center GPU. 10 May 2017. URL = https://devblogs. nvidia.com/parallelforall/inside-volta (data obrashcheniya: 01.09.2017).
  4. Eisymont L.K. Gibridnaya strategiya razvitiya ehlementnoj bazy // Otkrytye sistemy. SUBD. 2017. № 2. S. 8−11. URL = https:// www.osp.ru/os/2017/02/13052216 (data obrashcheniya: 01.09.2017).
  5. Mujtaba H. NVIDIA Announces Xavier Tegra SOC – Features Volta GPU With 7 Billion Transistors, 512 CUDA Cores and 8 ARM64 Custom Cores. Sep. 28, 2016. URL = http://wccftech.com/nvidia-xavier-soc-tegra-volta-gpu-announced (data obrashcheniya: 01.09.2017).
  6. Weinberg J. Quantifying locality in the memory access patterns of HPC Applications. University of California, San Diego. 2005. 50 p.
  7. Murphy R.C., Kogge P.M. On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications // IEEE Transactions on Computers. July 2007. V. 56. № 7. 9 p.
  8. Egawa R. et al. Early evaluation of the SX-ACE Processor SC14. November 2014. 2 p.
  9. Chernikov V.M., Viksne P.E., Sheluhin A.M., Shevchenko P.A., Panfilov A.P., Kosorukov D.E., Chernikov A.V. Semejstvo processorov obrabotki signalov s vektorno-matrichnoj arhitekturoj NeuroMatrix // Elektronnye komponenty. 2006. № 6. S. 79−84.
  10. Chernikov V.M., Viksne P.E., Sheluhin A.M., Panfilov A.P. Otechestvennye vysokoproizvoditel'nye processory cifrovoj obrabotki signalov vektorno-matrichnoj arhitektury, perspektivy razvitiya // Materialy konf. «Perspektivy razvitiya vysokoproizvoditel'nyh arhitektur. Istoriya, sovremennost' i budushchee otechestvennogo komp'yuterostroeniya». M.: ITMiVT im S.A. Lebedeva RAN. 2008. № 1. S. 52−59.
  11. IEEE 754-2008 – IEEE Standard for Floating-Point Arithmetic. © Copyright IEEE. 2008.

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