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Implementation on FPGA integer recursive digital filters without multipliers synthesized on not equidistant set of parameters


V.V. Artemiev – Post-graduate Student, Sedakov Scientific Research Institute of Measuring Systems

The article is devoted to the synthesis of recursive digital integer filter with the possibility of its implementation in FPGA. The article consists of six parts. The first part is an introduction. The second part provides an overview of the classical approaches of solving the problem of designing multiplierless digital filters. In the third part of the article proposes a method-integer nonlinear programming, allowing to solve the task on the specified set of parameters. Part four describes the hardware implementation on FPGA recursive digital filters without multiplier. In part five given the volume of the matrix space necessary for the implementation of digital filters synthesized on not equidistant set of parameters. The sixth part shows the performance of digital filters. In the seventh part the experimentally obtained frequency and phase response. The eighth part is the conclusion.

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