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Synthesis of gate characteristics on double gate SOI CMOS nanotransistors with longitudinally doping work area

Keywords:

N.V. Masalsky - Ph.D. (Phys.-Math.), Head of Sector, NIISI of the Russian Academy of Sciences (Moscow)


By means of numerical modeling electro-physical characteristics of double gate SOI CMOS nanotransistors with longitudinal graded-index doping work area are analyzed. The option of non-uniform and doping work area (including from a source) ‒ high-doping and low-doping areas is analyzed. In such structure the problem of hot carriers, roll-off of threshold voltage, restriction of level of subthreshold current is most successfully solved. Based on the received quasi analytical solution 2D of a Poisson equation numerically is calculated potential distributions in work area of the transistor by means of which are calculated: electric field, threshold voltage, subthreshold inclination and volt ampere characteristics. Results of calculations of distribution of potential are in data full good compliance of simulation received by means of commercially available software package by ATLASTM for 2D simulation of transistor structures. In operation one of possible approaches of development of multi threshold low-power electronics in relation to sub 25 nm for double gate SOI CMOS transistors is analyzed. The method of a choice of technological parameters of transistors with different thresholds taking into account their application for different circuitry applications is considered. By means of the HSPICE program response characteristics of valves of the inverter, 2NAND, 2NOR on two prototypes of transistors numerically are probed. In case of supply voltage of 1 V the minimum time delay of switching from all valves less than 1 ps corresponds to the inverter on low - threshold transistors, maximum - is characteristic of a valve 2NAND on highly ‒ threshold transistors which is more than 4 times higher than minimum. This valve is characterized by the largest active power which at a frequency of 100 GHz exceeds 36 mkW. The minimum static power makes 0,84 рW for the inverter on highly ‒ threshold transistors. In case of supply under voltage the time delay of valves behaves differently. For inverters on both types of transistors it practically doesn't increase up to voltage of 0,65 V. At the same time power consumptions of valves decrease approximately by two and a half times. The time delay of other valves is more sensitive to a supply voltage level. At the same time the tendency of lowering of power consumption remains. In total it is a premise for creation of the low-power circuit engineering functioning in the 100 th gigahertz range.

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May 29, 2020

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