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Increasing the failure tolerance of microprocessor systems to control flow errors based on architectural redundancy


S.L. Podvalny – Dr. Sc. (Eng.), Professor, Head of Department of Automated and Computing Systems,
Voronezh State Technical University
S.V. Tyurin – Ph. D. (Eng.), Associate Professor, Professor, Department of Automated and Computing Systems, Voronezh State Technical University
M.A. Khudyakov – Post-graduate Student, Department of Automated and Computing Systems,
Voronezh State Technical University

The article discusses the original method of rapid detection of random failures that violate the implementation of the work program in microprocessor systems. The error of program execution is a discrepancy between the command sequence, executed by the micro-processor after crash, and the working sequence of commands. The rapid detection of such failures is possible on the basis of archi-tectural improvements: the use of tagged memory program, the attribute «read command code», that is specifically generated by the microprocessor, and the organization of the additional interface, «handshake» between the microprocessor and program memory.
The essence of the proposed method of detection of random failures is the following. In the address space of the main (software) n bit storage device include additional single-bit storage device, that is each bit is a tag (named mark) that stores additional information for the distinction code that stored in the same cell of the primary (program) memory. Thus, the primary and the additional storage devices form a tagged program memory.
Microprocessor, in each cycle of turning to main memory, reports by the special signal about that, it is turned for the instruction code or the code of operand, at the same time the additional memory by default either confirms the correctness of rotation or reveals failure, that’s why we can see the formation of a signal of interruption of the microprocessor. Based on a preliminary analysis of the mi-croprocessor operating program, represented by binary codes, we can define the addresses of cells of the main storage device, which will contain command codes. For each cell it determine the amount of single values, which contain in the instruction code. Also if the amount of single values in the command code is even, then the corresponding bit of extra storage device must contain the unit (the command code is padded to odd). For all other code words of the work program, including useless cells of the main storage device, the code words complement to parity with the help of additional storage device. This markup of tagged memory can detect not only the flow of control errors, but single distortion of the data that read from the primary and secondary memory devices. Then, the CPU operating program, presented in the form of binary code is loaded into the main storage device, and additional storage is loaded by found values that complement to parity. The load of information into the basic and additional memory units can be produced both in the composition of microprocessor system and out of it.
In the operating mode of functioning the basic and additional memory devices form the united (n + 1) discharge memory unit, where n is the word length of the data bus of processor. To the address entrances of the basic and additional memory units moves the address codes, formed by processor on the tire of address.
The proposed method of detecting of the random failures, which disrupt the motion of the execution of working program, according to the preliminary estimations possesses have the large effectiveness (not more than the time of the fulfillment of two – three commands), it ensures the detection of 50−60% of the potential disturbances of the motion of the execution of working program and it requires for its realization not so many of equipment expenditures.

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