Publishing house Radiotekhnika

"Publishing house Radiotekhnika":
scientific and technical literature.
Books and journals of publishing houses: IPRZHR, RS-PRESS, SCIENCE-PRESS

Тел.: +7 (495) 625-9241


Design and implementation of FPGA to regular (2, DC) NB-LDPC decoders


A.V. Bashkirov – Ph. D. (Eng.), Associate Professor, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
A.V. Muratov – Dr. Sc. (Eng.), Professor, Head of Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
M.V. Khoroshaylova – Post-graduate Student, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University

NB-LDPC codes are decoded by an algorithm spread confidence (BP). Unlike the binary decoding LDPC, each message exchanged be-tween processing nodes in the factor graph - is an array of likelihood ratios corresponding to each of the possible elements of GF. In particular, the verification processing node (CN) is implemented as a forward-backward recursion, which requires a high and a large amount of memory ventel, and complexity grows as the square of the size of GF q and a linear function of the check node degree dc. The complexity of variable node processing (VN) increases as a linear function of q and the variable node degree dv. Difficulty VN important, as a large number of VNs need for common layered decoding scheme.
The complexity of the decoder are largely determines the code structure. Correcting the characteristics of medium length NB-LDPC block code can be improved by increasing q, but it significantly increases the decoder complexity.
This paper uses a shortened EMS algorithm that reduces the number of elements for GF processing at each step of decoding to q nm, nm < q at the same time provides high quality performance. Adapting the algorithm bubble check with low latency, making prefetching elementary CN (ECN), which simplifies the control of redundancy with little loss of functional performance at a low error rate. The new algorithm skimming offers reduced latency VN, to match the CN for a perfect alternation of an effective multi-level architecture of the decoding. To achieve the greatest possible effectiveness of pipelining proposed conflict-free access to memory data dependencies caused by the unstructured code. Overall (2, 4) is a regular (960, 480) GF (64) LDPC decoder for prototyping Xilinx Virtex 5 FPGA. The decoder provides bandwidth 9.76 MB / s and a good error correction performance.
Here are the decoder architecture and the FPGA prototype (2 dc) -regular NB-LDPC codes with high bandwidth and low latency. The new VN and CN design based on skimming, proactive and simplified control redundancy offer to reduce latency and enable efficient pipelining schedule. Memory conflict-free access eliminates the risk of data to avoid problems in the whole pipelining. These new methods have been applied in the design of the decoder 9.76 NB-LDPC MB / s on the Xilinx Virtex 5 FPGAs. The results show a good decoding performance down to low levels of error rate.

  1. Hocevar D.E. «A reduced complexity decoder architecture via layered decoding of LDPC codes,» in IEEE Workshop Signal Process. 2004.
  2. Huang J., Zhou S., and Willett P. «Nonbinary LDPC coding for multicarrier underwater acoustic communication», IEEE J. Sel. Areas Commun., 2008.
  3. Savin V. «Min-Max decoding for non binary LDPC codes», in Proc. (IEEE) International Symposium on Information Theory, Toronto. Canada. 2008.
  4. Bashkirov A.V., Korotkov L.N., Xoroshajlova M.V. Model' masshtabiruemogo LDPC-dekodera nizkoj moshhnosti s ispol'zovaniem algoritmicheskogo sinteza vy'sokogo urovnya // Vestnik VGTU. T. 12. № 1. 2016. S. 65−69.
  5. Bashkirov A.V., Savinkov A.Yu., Xoroshajlova M.V. Realizacziya LDPC-dekodera na massivno-parallel'ny'x vy'chislitel'ny'x ustrojstvax // Vestnik VGTU. T. 11. № 6. 2015. S. 97−99.
  6. Bashkirov A.V., Klimov A.I., Muratov A.V., Naumenko Yu.S., Czy'mbalyuk V.S. Perspektivy' modelirovaniya parametrov algoritmov pomexoustojchivogo kodirovaniya s vy'sokoj stepen'yu parallelizma pri pomoshhi apparatnoj platformy' na baze GPU // Zhurnal «Radiotexnika». M.: Radiotexnika Nomer 12. 2013. S. 26−29.
  7. Khoroshaylova M.V. THE LDPC DECODER ARCHITECTURE / Antropoczentricheskie nauki: innovaczionny'j vzglyad na obrazovanie i razvitie lichnosti. Materialy' II j Mezhdunar. nauchno-prakticheskoj konf.: V 2-x chastyax. Pod red. E'.P. Komarovoj. Voronezh. 2015. S. 227−228.
  8. Bashkirov A.V., Muratov A.V., Xoroshajlova M.V., Sitnikov A.V., Ermakov S.A. Nizkoplotnostny'e kody' maloj moshhnosti dekodirovaniya // Radiotexnika. 2016. № 5. S. 32−37.

© Издательство «РАДИОТЕХНИКА», 2004-2017            Тел.: (495) 625-9241                   Designed by [SWAP]Studio