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Algorithms low complexity decoding and architecture for non-binary low density codes

Keywords:

A.V. Bashkirov – Ph. D. (Eng.), Associate Professor, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University M.V. Horoshaylova – Post-graduate Student, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University


Using non-binary low density codes (NB-LDPC) can obtain better error correction performance than using their binary counterparts when code length is in reasonable expense of higher decoder complexity. High complexity is mainly due to complex calculations when processing check node and a large memory requirements. This article focuses on the development of decoding algorithms and VLSI architectures for NB-LDPC decoders. Coated topics include NB-LDPC decoders based on the Min-Max algorithm. Described softened processing circuit check node decoding algorithm Min-Max NB-LDPC. Using the property that every finite field element can be uniquely represented as a linear combination of elements in a minimal basis, all the entries in the vector posts are calculated at the same time effective way. This further reduces the need for memory capacity and computational complexity. Adoption of the proposed check node processing, the overall decoder can achieve a significantly higher efficiency than any existing structure. This article proposed for three NB-LDPC decoding algorithm and corresponding VLSI architecture codes, can reduce the computational complexity and memory requirements. The described model helped reduce VLSI design space decoders NB-LDPC based on several algorithms of low complexity decoding. However, these architectures can be further improved.
References:

 

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  2. Savin V. Min-Max decoding for non binary LDPC codes // Proc. IEEEIntl. Symp. onInfo. Theory. Toronto. Canada. Jul. 2008.
  3. Lin J., Sha J., Wang Z., Li  L. An efficient vlsi architecture for nonbinary LDPC decoders // IEEE Trans. on Circuits and Systems-II. 2010.
  4. Lin J., Sha J., Wang Z., LiL. Efficient decoder design for nonbinary quasicyclic LDPC codes // IEEE Trans. on Circuits and Systems‑I. 2010.
  5. Zhang X., Cai F. Efficient partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes // IEEE Trans. on Circuits and Systems-I. 2011.
  6. Bashkirov A.V., Belickijj A.M., Klimov A.I., Muratov A.V., Naumenko JU.S. Obzor osnovnykh tekhnologijj, realizujushhikh ehffektivnye metody pomekhoustojjchivogo kodirovanija, nechuvstvitelnykh k zaderzhke signala // Radiotekhnika. 2013. № 12. S. 30−33.
  7. Bashkirov A.V., Klimov A.I., Muratov A.V., Naumenko JU.S., Cymbaljuk V.S. Perspektivy modelirovanija parametrov algoritmov pomekhoustojjchivogo kodirovanija s vysokojj stepenju parallelizma pri pomoshhi apparatnojj platformy na baze GPU// Radiotekhnika. 2013. № 12. S. 26−29.

 

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