E. Yu. Doroshenko – Post-graduate Student, South-West State University (Kursk). E-mail: firstname.lastname@example.org
This paper investigates the issues of creating a high-performance computing device performing an arithmetic division of ternary balanced integers. The advantages of ternary balanced system for creating a computing device are marked. These are decrease of carrier propagation in the multi-bit numbers multiplication circuits, perform simple rounding dropping least significant bits, the ease of obtaining a negative value numbers etc. Examines existing division algorithms for numbers in the ternary balanced number system. It is noted that among the above algorithms Knuth algorithm allows to realize a divider with lower hardware costs. This explains the fact that this algorithm is the basis of the device algorithm.
Device for dividing numbers in ternary balanced system has a block structure. It consists of a data input unit, dividend register block, divisor register block, reminder register block, summing-subtraction block, unit of analysis and form of quotient digits, the sum-difference block, quotient register block and the control unit. Data input unit allows to input the ternary operand values, that proceed into dividend and divisor registers blocks. Summing-subtracting unit calculates the sum or the difference of the numbers proceeding at its input. Unit of analysis and form of quotient digits calculates the value of the next quotient digit. At the end of computing the result is stored in the registers blocks of quotient and remainder.
Proposed architecture can be used to create high-speed and high-performance digital systems.