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Design and test circuits for collection and processing systems information


V.A. Sklyar – Research Institute of Electronic Engineering. E-mail:
A.B. Achkasov – Ph.D. (Eng.), Research Institute of Electronic Engineering. E-mail:
K.V. Zolnikov – Research Institute of Electronic Engineering. E-mail:

OAO NIIET has developed the chip for the 16 channel 16bit1273ПВ10Т ADC. 1273ПВ10Тchipbelongs to the analog process class. Analog preprocessors are applied along with theDSPin the modern aircraft control systems, ground-baseddiagnostic systems for avionics, on-board data collection and processing systems. 1273ПВ10Тchip is a16 bitCMOS ADCwith sequential access interface. It has a signal/noise ratio of 77 database within the frequency band from 0 to 4 kHz. Each channelhas a programmableinput amplifierwith againrange from 0 to 38 dB.Conversion frequencycan be programmed forfour values: 64, 32, 16 or 8 kHz (whenthe inputclock frequencyis 16.384MHz). The serial port allows you to use the chip switched in cascade according to standard protocols DSP processors. Communication speed through the serial port is programmable that allows to use the chip with both fast and slow processors DSP. The block diagram is provided. An internal source forms the power supply. Internalvoltagesource comes to theoutput thatis used to connectan external capacitor. If thisoutput is used as a referencesource, it is mandatory to provide the buffering. Serial portprovidesa digitalconfiguration datainput and outputfrom the eightinternal registersand the output ofthe transformation results. This device containssix identicalchannels ofanalog data processing. An integratedamplifier with aprogrammable gain, which is aswitched capacitorcircuit,is partthe sigma-delta modulator. Out put voltage levelof the amplifiermust notexceed the maximuminput levelof sigma-deltamodulator. The built-in digital filter performs two important functions. At first, it's the removal of the analog modulator generated quantization noise outside the working frequency band and at second it's a thinning of flow of the high frequency single-bit words to the 15-bit stream of low frequency words. Antialiasing decimation filter is a digital filter with a characteristic in the form of sinc 3, which reduces the sampling frequency and increases the resolution from 1 to 15 bits. Z-transform transfer function expressed as a ratio [(1-Z-32) / (1-Z-1)] 3. Thisguaranteesaminimumgroupdelayof 25 ms. A specific feature of the circuit is a presence of programmable divider of the reference frequency which allows the user to reduce the frequency of an external clock signal. Clock divider allows the user to adjust the value of the clock frequency to the data. Thin ningdividerenables the user the flexibility toad just the value of the ADC samplingdeviceto the desired DSP program. Input and output data are transmittedina multi plextime division multiplexingformat(TDM).When reading data from the chip, each channel has a fixed time in tervalin which the data is transmitted. Circuit is designed to support up to eight devices in the cascade when connected to a single serial port. Serial port connection protocol is designed so that the addressing the device is contained in the sets of data transferred device. This allows generating a cascade without any additional hardware costs for the address and control signals. The cascade may be formed in the software and combined modes. Each channel of the chip can be used as a differential or single-ended input signal, which can be inverted by the input signal generator. The input signal can be connected to the DC level when the DC offset of the input signal is equal to the internal reference voltage level.

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