O. V. Nepomnyashchij – Ph.D. (Eng.), Associate Professor, Professor, Institute of Space and Information Technology, Siberian Federal University. E-mail: email@example.com
E. A. Vejsov – Ph.D. (Eng.), Professor, Military Training Center, Military Engineering Institute, Siberian Federal University. E-mail: Eveisov@sfu-kras.ru
A. S. Pravitel’ – Student, Institute of Space and Information Technology, Siberian Federal University. E-mail: firstname.lastname@example.org
VLSI as the part of special electronic equipment operating in difficult conditions of outer space or in areas of hostilities, are exposed to the combined effect of destabilizing factors (DF).
Ensuring a high level of reliability and stability of VLSI is achieved by using a range of measures at all stages of planning and preparation, for example, technology design, circuit design and design solutions. However increasing complexity of designing and growing demands for unification SE causes the development of new methods of systemic organization of single-crystal calculators. Solution can be found in the application of high-performance programmable logic integrated circuits (FPGA) with system of dynamic recon-figuration.
To ensure an adequate level of counteraction DF, the system operates in a dynamic reconfiguration mode and can change the contents of the FPGA clock domain at certain intervals in order to restore the cells as a result of failures. In the dynamic reconfiguration mode the crystal can change its internal logical structure in real time for a time significantly less runtime computing tasks between which there was a change structure.
In terms of unification, control system for various electromechanical unit, power unit or electronic unit besides high reliability, should provide maximum flexibility, which allows use the exact same VLSI for different units. In case of modular creation of special electronic equipment it is also possible to change the internal architecture of VLSI immediately during operation to ensure flexibility.
With a view to the practical implementation of the system with dynamic reconfiguration, the authors have developed a laboratory sample of management controller for synchronous motor with an electromagnetic reduction which applied as a part of the disclosure of the antenna unit into operating position.
When designing the controller is proposed bus-modular architecture of the central computer with dynamic reconfiguration. In order to improve system reliability and to prevent memory registers state changes as a result of the single failures in the developed controller is used method of triple redundancy at the processor level. In addition, each processing unit is configurable module and located in reconfigurable FPGA domains. Through this it is possible to restore the damaged CPU core as a result of DF by overwriting the contents of the respective FPGA domain.
The result of research is an approach to the architectural organization of self-healing SoC based on the principle of clock domains dynamic reconfiguration. Moreover, the proposed approach allows to unify and extend the functionality of special electronic equipment by automatic adjustment and adaptation to the current class of tasks by changing the topology of the control FPGA immediately during the operation.