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Application of Germanic technologies in CMOS microprocessors


V.A. Goryachev – Ph.D. (Phys.-Math.), Leading Research Scientist, NIISI RAS

For design of highly productive SOI CMOS microprocessors with low power separate features applications of germanium in the ICs constructional elements are considered. The component Ge increases speed of operation silicon chips and can combine both improving conductivity of copper connections, and new system of wireless data transfer. In comparison with silicon, at germanium more low tension of pn-transition (0.1 V  0.3 V against 0.6 V  0.7 V). It does germanium to more economic in respect of energy consumption. Implementation of Ge is interfaced to the considerable technological changes and enhancements, especially in case designing of big integrated microcircuits. The problem consists that in case creations of such structures use processes of self-organization nanocrystals (SON) germanium is necessary. As a whole procedure formation of structures contains normal, waste technological methods, but self-organization of nanocrystals – the nondeterministic process which results often are different from each other. Besides, the SOI transistors on silicon substrates represent n-type instruments, but p-type transistors for what the Ge-channel is created are necessary for CSOI of diagrams also. For overcoming of originating difficulties by the principal idea of experts in creation high-performance integrated circuits there is use of optical connections. Approximately during the same time frame representatives of the IBM company reported about the considerable advance on a way changeover electrical signals of optics communication. Their new superproductive photo-detector can be built in silicon chips. The device which creators call «the nanophoton avalanche photo-sensor element» (nanophotonic avalanche photo- detector), becomes a key component of future optical microprocessors. However processes of formation the planar hetero-structures including one-electron storage cells and one-electron transistors, as a rule, have four technological stages: a) thermal oxidation a silicon plate for receiving a layer of tunnel oxide SON separating a layer and the SOI device channel; b) sequential sedimentation by a method of the molecular and ray epitaxy (MRE) of thin layers of Ge (h = 0,50,9 nm) and Si layers (h = 530 nm); c) thermal oxidation of a high layer of Si before its contact with tunnel oxide; d) fast thermal annealing of structure in the inert environment for formation of a layer of nanocrystals of Ge. In later research of domestic authors from IFP the Siberian Branch the Russian Academy of Science simulation by the Monte-Carlo method analyzed formation of hetero-structures Si-Ge on the basis the filamentary nanocrystals which have been grown up on the mechanism of couples liquids-crystals. It is found that with a growth of axial hetero-junctions it is also impossible to receive atomarno uniform or smooth hetero-boundary of Si-Ge that is connected to gradual change composition of a drop the catalytic agent when switching flows. The second component providing high speed operation of the new field transistor, its topological structure with the channels surrounded from three sides by a lock is. Actually the channel germanic the SOI transistor is above the plane of the chip. All channels «are enveloped» by a lock, like the quantum transistor borrowed from development authors Russian Academy of Sciences Physico-Technological Institute. The similar structure can provide possibility of a positive control with a flow electronic holes via the transistor Ge-channel.

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