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Some problems of large-scale digital radiohologram array processing in high-resolution spaceborne synthetic aperture radar (SAR) imaging

Keywords:

T.A. Lepekhina, V.I. Nikolaev, M.A. Semyonov, E.F. Tolstov


Enlargement of SAR digital radiohologram volumes leads to the need of data processing rate improvement. Radiohologram processing in near-real time requires the ability of data processing time pre-estimation. The most computationally intensive operation is Fast Fourier Transform (FFT) calculation, FFT classic version performance having a complex dependence on a variety of factors. The FFT algorithm for general-purpose processors presented in this paper is designed to optimize the use of basic computer resources, ensuring high and stable processing speed. The algorithm is based on two concepts: special input/output data representation with the object to optimize utilization of arithmetic logic unit and cache memory data transfer rate, and predetermination of cache memory usage for maximum cache filling and minimum RAM using. After optimization, the most limiting factor is RAM memory bandwidth and at the same time there are at most three actual memory calls for strings of 2k elements, where k≤21. The developed algorithm can be used both in the imaging software for SAR ground segment and as part of the software for flight tests and validation.
References:
  1. Radiolokacionnye sistemy vozdushnojj razvedki. Deshifrirovanie radiolokacionnykh izobrazhenijj / Pod red. L.A. SHkolnogo. M.: Izd. VVIA im. N.E. ZHukovskogo. 2008.
  2. URL: http://ru.wikipedia.org/wiki/Bystroe_preobrazovanie_Fure (data obrashhenija: 27.04.2012).
  3. Intel® 64 and IA-32 Architectures. Optimization Reference Manual. URL: http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html (dataobrashhenija: 09.12.2011).
  4. Romanchenko V .Mikroarkhitektura Intel Sandy Bridge. URL: http://www.3dnews.ru/guide/intel_sandy_bridge_2/print (data obrashhenija: 03.02.2012).
  5. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A,2B & 2C: Instruction Set Reference. URL: http://download.intel.com/products/processor/manual/325383.pdf (data obrashhenija: 14.12.2011).
  6. Instruction tables. Lists of instruction latencies, throughputs and microoperation breakdowns for Intel, AMD and VIA CPUs. Agner Fog. Copenhagen University College of Engineering. Copyright © 1996 – 2011. Last updated 2011-06-08.

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