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Design techniques for static power reducing of nanometer VLSI


V.A. Bespalov, V.M. Dyakonov, A.V. Korshunov

One of challenge with CMOS technology scaling is the rapid increase of chip consumption power. It is needed to develop new design methodology to reduce power consumption. New methodology will minimize power without area or performance penalty. There are two kinds of power dissipation in synchronous CMOS VLSI: dynamic and static power. In this paper, we consider static power optimization methods. Static power dissipation includes three major components: subthreshold leakage, gate tunneling leakage and drain area leakage (including reverse bias leakage, GIDL and DIBL). The subthreshold leakage, Isub, dominates other types of leakage in VLSI for technology before 65nm. We describe methods of minimization leakage power for physical, schematic and logic stages of nanometer VLSI design flow. This paper describes techniques and issues for design techniques for static power reducing of VLSI. We are considering such schematic techniques as sleep approach, stack effect, VTCMOS and MTCMOS. Also we describe new approaches that allow save signal value in standby mode of VLSI. These approaches are including sleepy stack; sleepy-keeper; dual-sleep. We are considering such logic techniques as power gating (coarse grain MTCMOS) and clustering voltage scaling (CVS). This approaches allowed significantly reduced leakage for nanometer CMOS VLSI. In conclusion we are analyzing the efficiency of static power optimization methods. Also we are considering the efficiency power optimization methods for nanometer CMOS technology.

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