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Methods of Minimizing Phase Noise in Ku-Range Hybrid Frequency Synthesizer with Fast Frequency Hopping Mode


I.A. Grigoryev

This paper introduces the different synthesizers configurations modeling results for upconverter module in Ku-band synthesizer, which is fully described in paper [1]. The different approaches including direct frequency synthesis based on multiplying reference signal and indirect frequency synthesis based on PLL was deeply analyzed. Achieved results leads to some features and issues of all considered schemes. The key feature of direct analog synthesis is near to ideal phase noise distribution which corresponds to phase noise obtained by reference signal phase noise multiplying. But using multipliers as a main component of synthesizer system lead to physical dimension increase in case of wide frequency range requirements or achieving frequency values which can’t obtained using multiplying only. PLL based synthesizers can be used to solve a list of challenges connected with achieving required frequency list, decreasing power consumption and physical dimensions. But the results obtained in PLL modeling shows that the most noisy component in PLL loop is the phase frequency detector which generate phase noise multiplied by the in loop division factor. Obtained results analysis shows that the optimal solution for phase noise decreasing in phase frequency detector is achieving comparison frequency by mixing VCO signal and reference multiplied by N signal. Using this approach we achieved multiplied reference signal phase noise as a main component in the in-loop phase noise distribution. The PFD is a component with a much smaller contribution in comparison with multiplied reference phase noise. Also this approach provides the possibility to significantly decrease in-loop phase noise and maximum using both of direct synthesis and PLL configuration benefits.
June 24, 2020
May 29, 2020

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