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Increase of Fault Tolerance of Cache-memory in Microprocessor Systems

Keywords:

V.N. Zakharov, B.Z. Shmeilin


With growth of integration degree of manufacturing techniques microprocessors become more and more sensitive to the transient errors which reasons are the most various phenomena in environment. As placed on a die of the microprocessor the cache-memory contains the big share of transistors of a die it is most subject to influence of such errors among other components of microprocessor system. In article vulnerability to transient errors of cache-memory data items is researched, the behavior of data items model from the point of view of their vulnerability is offered. In this model some lifetime phases for each data element differ and further these phases are divided on two groups: vulnerable and non-vulnerable phases. A vulnerable phase is characterized by the fact that errors that occurred during this phase have the potential to propagate either to the processor (by load operations) or to the second level cache-memory (via line replacement). On the basis of data items behavior model various methods of lowering of vulnerability without essential loss of productivity of the microprocessor system are offered. In the given operation it is shown that implementation of these methods depends on character of the application
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